BG

Blaine D. Gaither

HP HP: 51 patents #155 of 16,619Top 1%
HE Hewlett Packard Enterprise: 9 patents #280 of 4,473Top 7%
BU Burroughs: 2 patents #155 of 604Top 30%
WT Western Digital Technologies: 1 patents #1,787 of 3,180Top 60%
📍 Fort Collins, CO: #23 of 3,421 inventorsTop 1%
🗺 Colorado: #234 of 40,980 inventorsTop 1%
Overall (All Time): #35,814 of 4,157,543Top 1%
63
Patents All Time

Issued Patents All Time

Showing 26–50 of 63 patents

Patent #TitleCo-InventorsDate
8176293 Method and system for moving active virtual partitions between computers John A. Morrison 2012-05-08
8051250 Systems and methods for pushing data Darel N. Emmot, Judson E. Veazey, Benjamin D. Osecky 2011-11-01
7861228 Variable delay instruction for implementation of temporal redundancy Benjamin D. Osecky 2010-12-28
7774551 Hierarchical cache coherence directory structure Verna Knapp 2010-08-10
7765363 Mask usable for snoop requests Benjamin D. Osecky, Gerald J. Kaufman, Jr. 2010-07-27
7739478 Multiple address sequence cache pre-fetching Judson E. Veazey 2010-06-15
7600079 Performing a memory write of a data unit without changing ownership of the data unit Judson E. Veazey, Patrick Knebel 2009-10-06
7584405 Fault-detecting computer system Benjamin D. Osecky 2009-09-01
7376799 System for reducing the latency of exclusive read requests in a symmetric multi-processing system Judson E. Veazey 2008-05-20
7370209 Systems and methods for increasing the difficulty of data sniffing Bret A. McKee 2008-05-06
7353336 External RAID-enabling cache 2008-04-01
7310708 Cache system with groups of lines and with coherency for both single lines and groups of lines 2007-12-18
7237084 Method and program product for avoiding cache congestion by offsetting addresses while allocating memory Douglas V. Larson, Richard G. Fowles, Benjamin D. Osecky 2007-06-26
7096320 Computer performance improvement by adjusting a time used for preemptive eviction of cache entries Benjamin D. Osecky 2006-08-22
7085887 Processor and processor method of operation 2006-08-01
7051195 Method of optimization of CPU and chipset performance by support of optional reads by CPU and chipset Robert J. Brooks 2006-05-23
7032074 Method and mechanism to use a cache to translate from a virtual bus to a physical bus 2006-04-18
6950135 Method and apparatus for gathering three dimensional data with a digital imaging system Bret A. McKee, Michael J. Mahon 2005-09-27
6938071 Fault tolerant storage system having an interconnection fabric that also carries network traffic Bret A. McKee 2005-08-30
6892173 Analyzing effectiveness of a computer cache by estimating a hit rate based on applying a subset of real-time addresses to a model of the cache Robert B. Smith 2005-05-10
6889244 Method and apparatus for passing messages using a fault tolerant storage system Bret A. McKee 2005-05-03
6813691 Computer performance improvement by adjusting a count used for preemptive eviction of cache entries Benjamin D. Osecky 2004-11-02
6810465 Limiting the number of dirty entries in a computer cache Benjamin D. Osecky 2004-10-26
6792550 Method and apparatus for providing continued operation of a multiprocessor computer system after detecting impairment of a processor cooling device Benjamin D. Osecky 2004-09-14
6721848 Method and mechanism to use a cache to translate from a virtual bus to a physical bus 2004-04-13