Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6998658 | Twin NAND device structure, array operations and fabrication method | Seiki Ogura, Tomoko Ogura, Kimihiro Satoh | 2006-02-14 |
| 6900098 | Twin insulator charge storage device operation and its fabrication method | Seiki Ogura, Kimihiro Satoh | 2005-05-31 |
| 6838344 | Simplified twin monos fabrication method with three extra masks to standard CMOS | Kimihiro Satoh, Seiki Ogura | 2005-01-04 |
| 6825084 | Twin NAND device structure, array operations and fabrication method | Seiki Ogura, Tomoko Ogura, Kimihiro Satoh | 2004-11-30 |
| 6759290 | Stitch and select implementation in twin MONOS array | Tomoko Ogura, Seiki Ogura, Kimihiro Satoh | 2004-07-06 |
| 6756271 | Simplified twin monos fabrication method with three extra masks to standard CMOS | Kimihiro Satoh, Seiki Ogura | 2004-06-29 |
| 6707079 | Twin MONOS cell fabrication method and array organization | Kumihiro Satoh, Seiki Ogura | 2004-03-16 |
| 6670240 | Twin NAND device structure, array operations and fabrication method | Seiki Ogura, Tomoko Ogura, Kimihiro Satoh | 2003-12-30 |
| 6631088 | Twin MONOS array metal bit organization and single cell operation | Seiki Ogura, Tomoko Ogura | 2003-10-07 |
| 6531350 | Twin MONOS cell fabrication method and array organization | Kimihiro Satoh, Seiki Ogura | 2003-03-11 |
| 6477088 | Usage of word voltage assistance in twin MONOS cell during program and erase | Seiki Ogura, Tomoko Ogura | 2002-11-05 |
| 6418062 | Erasing methods by hot hole injection to carrier trap sites of a nonvolatile memory | Yutaka Hayashi, Seiki Ogura | 2002-07-09 |