TS

Thomas E. Seidel

GE Genus: 13 patents #2 of 76Top 3%
AT AT&T: 3 patents #5,550 of 18,772Top 30%
BL Bell Telephone Laboratories: 2 patents #297 of 1,445Top 25%
SE Sematech: 2 patents #22 of 123Top 20%
AI Aixtron: 1 patents #31 of 62Top 50%
HG Hyperstone Gmbh: 1 patents #8 of 17Top 50%
SG Solarworld Innovations Gmbh: 1 patents #19 of 49Top 40%
📍 Konstanz, FL: #1 of 1 inventorsTop 100%
Overall (All Time): #122,874 of 4,157,543Top 3%
30
Patents All Time

Issued Patents All Time

Showing 26–30 of 30 patents

Patent #TitleCo-InventorsDate
5102816 Staircase sidewall spacer for improved source/drain architecture V. Reddy Manukonda 1992-04-07
4653177 Method of making and selectively doping isolation trenches utilized in CMOS devices Joseph Lebowitz 1987-03-31
4643804 Forming thick dielectric at the bottoms of trenches utilized in integrated-circuit devices William T. Lynch 1987-02-17
4364778 Formation of multilayer dopant distributions in a semiconductor Harry J. Leamy 1982-12-21
4258078 Metallization for integrated circuits George K. Celler 1981-03-24