Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7337414 | Logical equivalence verifying device, method, and computer-readable medium thereof | Hiroji Takeyama, Takeo Nakamura, Mitsuru Satou, Yuki Kumon, Miki Takagi | 2008-02-26 |
| 7143375 | Logical equivalence verifying device, method and computer readable medium thereof | Hiroji Takeyama, Takeo Nakamura, Mitsuru Satou, Yuki Kumon, Miki Takagi | 2006-11-28 |
| 6260179 | Cell arrangement evaluating method, storage medium storing cell arrangement evaluating program, cell arranging apparatus and method, and storage medium storing cell arranging program | Keiko Ohsawa | 2001-07-10 |
| 6240541 | Interactive circuit designing apparatus which displays a result of component placement and wire routing from a layout design unit | Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno +6 more | 2001-05-29 |
| 6226778 | Method and apparatus for determining locations of circuit elements including sequential circuit elements | Tadashi Konno, Keiko Ohsawa | 2001-05-01 |
| 5892685 | Packaging design system for an LSI circuit | Hiroyuki Sugiyama, Ryouichi Yamashita | 1999-04-06 |
| 5889677 | Circuit designing apparatus of an interactive type | Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno +6 more | 1999-03-30 |
| 5787268 | Interactive circuit designing apparatus | Yaroku Sugiyama, Hiroyuki Sugiyama, Noriyuki Ito, Ryouichi Yamashita, Yasunori Abe | 1998-07-28 |