Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8315846 | Design data merging apparatus and design data merging method | Takeo Nakamura, Junko Taira | 2012-11-20 |
| 7337414 | Logical equivalence verifying device, method, and computer-readable medium thereof | Terunobu Maruyama, Hiroji Takeyama, Takeo Nakamura, Mitsuru Satou, Yuki Kumon | 2008-02-26 |
| 7143375 | Logical equivalence verifying device, method and computer readable medium thereof | Terunobu Maruyama, Hiroji Takeyama, Takeo Nakamura, Mitsuru Satou, Yuki Kumon | 2006-11-28 |
| 7086016 | Method and apparatus for verifying logical equivalency between logic circuits | Kazuhiro Matsuzaki, Hiroji Takeyama, Hiroshi Noguchi | 2006-08-01 |
| 6678871 | Circuit designing apparatus, circuit designing method and timing distribution apparatus | Hiroji Takeyama, Koichi Itaya, Takehiro Yamazaki | 2004-01-13 |
| 6618834 | Circuit designing apparatus, circuit designing method and timing distribution apparatus | Hiroji Takeyama, Koichi Itaya, Takehiro Yamazaki | 2003-09-09 |
| 6240541 | Interactive circuit designing apparatus which displays a result of component placement and wire routing from a layout design unit | Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno +6 more | 2001-05-29 |
| 5889677 | Circuit designing apparatus of an interactive type | Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno +6 more | 1999-03-30 |