Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8539412 | Macro layout verification appartus | Masashi Arayama | 2013-09-17 |
| 8453077 | Circuit designing method and circuit designing system | Yasuo Amano | 2013-05-28 |
| 8286117 | Macro layout verification apparatus to detect error when connecting macro terminal in LSI design layout | Masashi Arayama | 2012-10-09 |