Issued Patents All Time
Showing 76–84 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8181132 | Validating one or more circuits using one or more grids | Jawahar Jain, Subramanian K. Iyer, Thomas W. Sidle | 2012-05-15 |
| 7743350 | Verifying one or more properties of a design using SAT-based BMC | — | 2010-06-22 |
| 7685471 | System and method for detecting software defects | Sreeranga P. Rajan, Oksana Tkachuk, Indradeep Ghosh | 2010-03-23 |
| 7546563 | Validating one or more circuits using one of more grids | Jawahar Jain, Subramanian K. Iyer, Thomas W. Sidle | 2009-06-09 |
| 7458046 | Estimating the difficulty level of a formal verification problem | Indradeep Ghosh | 2008-11-25 |
| 7290230 | System and method for verifying a digital design using dynamic abstraction | — | 2007-10-30 |
| 7194710 | Scheduling events in a boolean satisfiability (SAT) solver | Rajarshi Mukherjee | 2007-03-20 |
| 7076712 | Generating a test sequence using a satisfiability technique | Michael Hsiao, Jawahar Jain | 2006-07-11 |
| 7032192 | Performing latch mapping of sequential circuits | Rajarshi Mukherjee, Jawahar Jain, Kelvin Kwok-Cheung Ng | 2006-04-18 |