Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5896501 | Multiprocessor system and parallel processing method for processing data transferred between processors | Masayuki Ikeda, Shigeru Nagasawa, Haruhiko Ueno, Naoki Shinjo, Teruo Utsumi +4 more | 1999-04-20 |
| 5832261 | Barrier synchronizing mechanism for a parallel data processing control system | Masayuki Katori, Masayuki Ikeda, Shigeru Nagasawa, Hiroshi Komatsuda | 1998-11-03 |
| 5822785 | Data transfer using local and global address translation and authorization | Masayuki Ikeda, Shigeru Nagasawa, Naoki Shinjo, Teruo Utsumi, Masami Dewa +2 more | 1998-10-13 |
| 5765009 | Barrier synchronization system in parallel data processing | — | 1998-06-09 |
| 5664104 | Transfer processor including a plurality of failure display units wherein a transfer process is prohibited if failure is indicated in a failure display unit | Naoki Shinjo, Shigeru Nagasawa, Masayuki Ikeda, Haruhiko Ueno, Teruo Utsumi +3 more | 1997-09-02 |
| 5652905 | Data processing unit | Naoki Shinjo, Shigeru Nagasawa, Masayuki Ikeda, Haruhiko Ueno, Teruo Utsumi +3 more | 1997-07-29 |
| 5634071 | Synchronous processing method and apparatus for a plurality of processors executing a plurality of programs in parallel | Masami Dewa, Shigeru Nagasawa, Masayuki Ikeda, Haruhiko Ueno, Naoki Shinjo +3 more | 1997-05-27 |
| 5625846 | Transfer request queue control system using flags to indicate transfer request queue validity and whether to use round-robin system for dequeuing the corresponding queues | Kazushige Kobayakawa, Shigeru Nagasawa, Masayuki Ikeda, Haruhiko Ueno, Naoki Shinjo +2 more | 1997-04-29 |
| 5623688 | Parallel processing system including instruction processor to execute instructions and transfer processor to transfer data for each user program | Masayuki Ikeda, Shigeru Nagasawa, Naoki Shinjo, Teruo Utsumi, Masami Dewa +2 more | 1997-04-22 |
| 5621395 | Networking apparatus which detects a stoppage of data transfer in a processing apparatus on a data origination side and then cancels the corresponding path in the switching unit | Akihito Kiyaji, Hiroshi Komatsuda, Masayuki Katori | 1997-04-15 |
| 5592680 | Abnormal packet processing system | Teruo Utsumi, Shigeru Nagasawa, Masayuki Ikeda, Naoki Shinjo, Masami Dewa +2 more | 1997-01-07 |
| 5572679 | Multiprocessor system transferring abnormality detection signal generated in networking apparatus back to processor in parallel with data transfer route | Masayuki Katori | 1996-11-05 |
| 5572680 | Method and apparatus for processing and transferring data to processor and/or respective virtual processor corresponding to destination logical processor number | Masayuki Ikeda, Shigeru Nagasawa, Naoki Shinjo, Teruo Utsumi, Masami Dewa +2 more | 1996-11-05 |
| 5557744 | Multiprocessor system including a transfer queue and an interrupt processing unit for controlling data transfer between a plurality of processors | Kazushige Kobayakawa, Shigeru Nagasawa, Masayuki Ikeda, Haruhiko Ueno, Naoki Shinjo +2 more | 1996-09-17 |