Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6405354 | Method and apparatus to optimize power wiring layout and generate wiring layout data for a semiconductor integrated circuit | Takayuki Matsuzawa, Takanori Nawa | 2002-06-11 |
| 6035111 | Manufacturing method and apparatus of a semiconductor integrated circuit device | Rieko Suzuki, Kiyoshi Saida, Eiji Fujine, Yoshihiro Kamiya, Yoshitaka Uchida +5 more | 2000-03-07 |
| 5618744 | Manufacturing method and apparatus of a semiconductor integrated circuit device | Rieko Suzuki, Kiyoshi Saida, Eiji Fujine, Yoshihiro Kamiya, Yoshitaka Uchida +5 more | 1997-04-08 |