Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9672076 | Scheduling process on a processor or an accelerator on a system driven by battery based on processing efficiency and power consumption | Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Naoki Odate +2 more | 2017-06-06 |
| 9563465 | Multi-task scheduling method for assigning threads based on time slices to multi-core processors and multi-core processor system therefor | Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Naoki Odate +1 more | 2017-02-07 |
| 9483101 | Multicore processor system and power control method | Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara, Naoki Odate +2 more | 2016-11-01 |
| 9471123 | Reducing unnecessary power consumed by peripheral devices while displaying a moving image | Tetsuo Hiraki, Hiromasa Yamauchi, Koichiro Yamashita, Naoki Odate, Takahisa Suzuki +1 more | 2016-10-18 |
| 9241295 | Communication apparatus and communication method | Toshiya Otomo, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara | 2016-01-19 |
| 9164823 | Resetting a peripheral driver and prohibiting writing into a register retaining data to be written into a peripheral on exceeding a predetermined time period | Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara | 2015-10-20 |
| 9043507 | Information processing system | Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara | 2015-05-26 |
| 8990516 | Multi-core shared memory system with memory port to memory space mapping | Koichiro Yamashita | 2015-03-24 |
| 7133973 | Arithmetic processor | Hiroshi Okano | 2006-11-07 |
| 7028151 | Information processing device equipped with improved address queue register files for cache miss | Satoshi Imai, Atsuhiro Suga | 2006-04-11 |
| 6931508 | Device and method for information processing | Hiroshi Okano | 2005-08-16 |