Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6002155 | Semiconductor integrated circuit with protection circuit against electrostatic breakdown and layout design method therefor | Isao Amano | 1999-12-14 |
| 5672895 | Semiconductor integrated circuit with protection circuit against electrostatic breakdown and layout design method therefor | Takashi Iida, Satoru Sumi, Hiroshi Shimizu, Isao Amano, Tetsuya Nakajima | 1997-09-30 |
| 5500542 | Semiconductor integrated circuit with protection circuit against electrostatic breakdown and layout design method therefor | Takashi Iida, Satoru Sumi, Hiroshi Shimizu, Isao Amano, Tetsuya Nakajima | 1996-03-19 |
| 4888623 | Semiconductor device with PN junction isolation for TTL or ECL circuits | Hiromu Enomoto, Yasushi Yasuda, Yoshiki Shimauchi | 1989-12-19 |
| 4810908 | Semiconductor logic circuit comprising clock driver and clocked logic circuit | Hirokazu Suzuki, Shinji Saito | 1989-03-07 |
| 4774620 | Logic circuit | Hiromu Enomoto, Yasushi Yasuda, Masao Kumagai | 1988-09-27 |
| 4703202 | Two-stage gate circuit providing inverted and non-inverted outputs | Hiromu Enomoto, Yasushi Yasuda, Masao Kumagai | 1987-10-27 |
| 4680600 | Semiconductor device | Hiromu Enomoto, Yasushi Yasuda | 1987-07-14 |
| 4567380 | Schmitt trigger circuit | Yasushi Yasuda, Hiromu Enomoto, Yoshiki Shimauchi | 1986-01-28 |