Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7474143 | Voltage generator circuit and method for controlling thereof | Hajime Sato, Syuichi Saito | 2009-01-06 |
| 7330043 | Semiconductor device and test method for the same | Seiji Yamamoto, Hirosuke Koumyoji, Tohru Yasuda, Mikio Ishikawa, Isaya Sobue +3 more | 2008-02-12 |
| 7095273 | Voltage generator circuit and method for controlling thereof | Hajime Sato, Syuichi Saito | 2006-08-22 |
| 6885212 | Semiconductor device and test method for the same | Seiji Yamamoto, Hirosuke Koumyoji, Tohru Yasuda, Mikio Ishikawa, Isaya Sobue +3 more | 2005-04-26 |
| 6762617 | Semiconductor device having test mode entry circuit | Yoshiharu Kato | 2004-07-13 |
| 6651196 | Semiconductor device having test mode entry circuit | Yoshiharu Kato | 2003-11-18 |
| 5747837 | Semiconductor device having input protective function | Tomio Nakano, Teruo Seki | 1998-05-05 |
| 5719812 | Semiconductor memory including bit line reset circuitry and a pulse generator having output delay time dependent on type of transition in an input signal | Teruo Seki, Shinzi Nagai | 1998-02-17 |
| 5631865 | Data outputting circuit for semiconductor memory device | Masaharu Kagohashi | 1997-05-20 |
| 5475639 | Semiconductor memory device with improved speed for reading data | Teruo Seki, Shinji Nagai, Tadashi Ozawa | 1995-12-12 |
| 5453956 | Load generator used in semiconductor memory device | Teruo Seki, Masaharu Kagohashi | 1995-09-26 |
| 5097159 | Delay circuit for delaying an output signal relative to an input signal for a specified time interval | Teruo Seki, Sinzi Nagai | 1992-03-17 |