Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8464004 | Information processing apparatus, memory control method, and memory control device utilizing local and global snoop control units to maintain cache coherency | Go Sugizaki, Naozumi Aoki, Tsuyoshi Motokurumada | 2013-06-11 |
| 8446020 | Multi-chip module | Masateru Koide, Daisuke Mizutani, Hideo Yamashita, Iwao Yamazaki, Masayuki Kato +2 more | 2013-05-21 |
| 7925870 | Return target address prediction by moving entry pointer to return stack popped at completion to deeper one at return instruction fetch | Masaki Ukai | 2011-04-12 |
| 7765387 | Program counter control method and processor thereof for controlling simultaneous execution of a plurality of instructions including branch instructions using a branch prediction mechanism and a delay instruction for branching | Ryuichi Sunayama, Kuniki Morita | 2010-07-27 |
| 7603545 | Instruction control method and processor to process instructions by out-of-order processing using delay instructions for branching | Ryuichi Sunayama | 2009-10-13 |
| 7350062 | Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal | Masaki Ukai, Kyoko Tashima | 2008-03-25 |
| 7278010 | Instruction execution apparatus comprising a commit stack entry unit | Yasunobu Akizuki | 2007-10-02 |
| 7246204 | Pre-fetch control device, data processing apparatus and pre-fetch control method | Yuji Shirahige, Tsuyoshi Motokurumada, Masaki Ukai | 2007-07-17 |
| 7036003 | Instruction processing device and method for controlling branch instruction accompanied by mode change | Ryuichi Sunayama | 2006-04-25 |
| 6993638 | Memory access device and method using address translation history table | Masaki Ukai | 2006-01-31 |
| 6912650 | Pre-prefetching target of following branch instruction based on past history | Masaki Ukai | 2005-06-28 |
| 6898698 | Device predicting a branch of an instruction equivalent to a subroutine return and a method thereof | Ryuichi Sunayama, Masaki Ukai | 2005-05-24 |
| 6851043 | Branch instruction execution control apparatus | — | 2005-02-01 |
| 6789185 | Instruction control apparatus and method using micro program | Norihito Gomyo | 2004-09-07 |
| 6754814 | Instruction processing apparatus using a microprogram that implements a re-reading operation by controlling early loading of instructions | Hiroki Narita | 2004-06-22 |
| 6606696 | Virtual storage address space access control | Hiroshi Kawano | 2003-08-12 |
| 6571329 | Detection of overwrite modification by preceding instruction possibility of fetched instruction code using fetched instructions counter and store target address | Masaki Ukai | 2003-05-27 |
| 6535943 | Information processing device enabling floating interrupt to be pending and a method executing an interrupt condition change instruction | Syuuei Hatamori | 2003-03-18 |
| 6532534 | Information processing apparatus provided with branch history with plurality of designation ways | Ryuichi Sunayama | 2003-03-11 |
| 6530013 | Instruction control apparatus for loading plurality of instructions into execution stage | Michiharu Hara | 2003-03-04 |
| 6530016 | Predicted return address selection upon matching target in branch history table with entries in return address stack | Masaki Ukai, Kyoko Tashima | 2003-03-04 |
| 6502186 | Instruction processing apparatus | — | 2002-12-31 |
| 6421771 | Processor performing parallel operations subject to operand register interference using operand history storage | — | 2002-07-16 |
| 6016541 | Instruction controlling system and method thereof | Kyoko Tashima, Takeo Asakawa | 2000-01-18 |
| 5923864 | Virtual storage address space access control system including auxiliary translation lookaside buffer | — | 1999-07-13 |