Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12175283 | Hardware-accelerated computing system | Sourav Roy, Arvind Kaushik, Sneha Mishra | 2024-12-24 |
| 11861403 | Method and system for accelerator thread management | Sourav Roy, Arvind Kaushik, Sneha Mishra, Howard Dewey Owens | 2024-01-02 |
| 10817413 | Hardware-based memory management for system-on-chip (SoC) integrated circuits that identify blocks of continuous available tokens needed to store data | Kaushik Arvind, Amrit P. Singh, Mohit Gupta | 2020-10-27 |
| 9900390 | Method and apparatus for controlling wake events in a data processing system | David C. Holloway, Benjamin C. Eckermann, Craig C. Hunter, Bryan D. Marietta, David W. Todd | 2018-02-20 |
| 9207979 | Explicit barrier scheduling mechanism for pipelining of stream processing algorithms | James C. Holt, David B. Kramer, William C. Moyer | 2015-12-08 |
| 8700878 | Event triggered memory mapped access | William Schwarz, Jason T. Nearing, Zheng Xu | 2014-04-15 |
| 8509370 | Phase locked loop device and method thereof | Gayathri A. Bhagavatheeswaran, Arvind Raman, Hector Sanchez | 2013-08-13 |
| 7107489 | Method and apparatus for debugging a data processing system | Tan Nhat Dao, Jerome Hannah | 2006-09-12 |
| 7013409 | Method and apparatus for debugging a data processing system | Tan Nhat Dao, Jerome Hannah | 2006-03-14 |
| 6842895 | Single instruction for multiple loops | Pascal Renard | 2005-01-11 |
| 6751759 | Method and apparatus for pipeline hazard detection | Xiao Sun, Chi Huy Duong | 2004-06-15 |
| 5442576 | Multibit shifting apparatus, data processor using same, and method therefor | Kin K. Chau-Lee | 1995-08-15 |
| 5363322 | Data processor with an integer multiplication function on a fractional multiplier | Peter A. Percosan | 1994-11-08 |
| 5303355 | Pipelined data processor which conditionally executes a predetermined looping instruction in hardware | Kin K. Chau-Lee | 1994-04-12 |
| 5001665 | Addressing technique for providing read, modify and write operations in a single data processing cycle with serpentine configured RAMs | Charles D. Thompson | 1991-03-19 |
| 4785411 | Cascade filter structure with time overlapped partial addition operations and programmable tap length | Charles D. Thompson, Bradley J. Martin, Garth D. Hillman | 1988-11-15 |
| 4766561 | Method and apparatus for implementing multiple filters with shared components | Charles D. Thompson | 1988-08-23 |