Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8261250 | Single-chip multiprocessor with clock cycle-precise program scheduling of parallel execution | Boris A. Babaian, Vladimir Yu. Volkonskiy, Sergey A. Rozhkov, Vladimir V. Tikhorsky, Feodor A. Gruzdov +2 more | 2012-09-04 |
| 7895587 | Single-chip multiprocessor with clock cycle-precise program scheduling of parallel execution | Boris A. Babaian, Vladimir Yu. Volkonskiy, Sergey A. Rozhkov, Vladimir V. Tikhorsky, Feodor A. Gruzdov +2 more | 2011-02-22 |
| 7143401 | Single-chip multiprocessor with cycle-precise program scheduling of parallel execution | Boris A. Babaian, Vladimir Yu. Volkonskiy, Sergey A. Rozhkov, Vladimir V. Tikhorsky, Feodor A. Gruzdov +2 more | 2006-11-28 |
| 7003650 | Method for prioritizing operations within a pipelined microprocessor based upon required results | Boris A. Babaian, Valeri G. Gorokhov, Feodor A. Gruzdov, Vladimir V. Rudometov, Valdimir Y. Volkonsky | 2006-02-21 |
| 6560775 | Branch preparation | Alexander M. Artymov, Boris A. Babaian, Feodor A. Gruzdov, Alexey P. Lizorkin, Evgeny Z. Stolyarsky | 2003-05-06 |
| 6549903 | Integrity of tagged data | Boris A. Babaian, Feodor A. Gruzdov, Vladimir Y. Volkonsky | 2003-04-15 |
| 6243822 | Method and system for asynchronous array loading | Boris A. Babaian, Mikhail L. Chudakov, Oleg A. Konopleff, Andrey A. Vechtomov | 2001-06-05 |
| 5983336 | Method and apparatus for packing and unpacking wide instruction word using pointers and masks to shift word syllables to designated execution units groups | Alexander M. Artyomov, Alexey P. Lizorkin, Vladimir V. Rudometov, Leonid N. Nazarov | 1999-11-09 |
| 5958048 | Architectural support for software pipelining of nested loops | Boris A. Babaian, Feodor A. Gruzdov, Vladimir S. Volin, Vladimir Yu. Volkonski | 1999-09-28 |
| 5889985 | Array prefetch apparatus and method | Boris A. Babaian, Valeri G. Gorokhov, Feodor A. Gruzdov, Vladimir Yu. Volkonski | 1999-03-30 |
| 5794029 | Architectural support for execution control of prologue and eplogue periods of loops in a VLIW processor | Boris A. Babaian, Valeri G. Gorokhov, Feodor A. Gruzdov, Vladimir Yu. Volkonski | 1998-08-11 |