Issued Patents All Time
Showing 151–175 of 319 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8316287 | Low-density parity check codes for holographic storage | Nedeljko Varnica, Seo-How Low, Gregory Burd | 2012-11-20 |
| 8316206 | Pilot placement for non-volatile memory | Xueshi Yang, Pantas Sutardja | 2012-11-20 |
| 8315132 | Defect detection design | Shaohua Yang, Hongwei Song, Xueshi Yang, Hongxin Song | 2012-11-20 |
| 8312354 | Method and apparatus for improved performance of iterative decoders on channels with memory | Nedeljko Varnica, Nitin Nangare, Gregory Burd | 2012-11-13 |
| 8312341 | Interleaved error correction coding for channels with non-uniform SNRs | Nedeljko Varnica, Gregory Burd | 2012-11-13 |
| 8306245 | Multi-mode audio amplifiers | — | 2012-11-06 |
| 8307268 | Iterative decoder systems and methods | Panu Chaichanavong, Nedeljko Varnica, Nitin Nangare, Gregory Burd | 2012-11-06 |
| 8301976 | Defect detector for holographic storage systems | Shaohua Yang | 2012-10-30 |
| 8300339 | Method and system for compensating for adjacent tracks during reading of data | Nitin Nangare, Gregory Burd | 2012-10-30 |
| 8296635 | Architecture and control of Reed-Solomon error-correction decoding | Siu-Hung Fred Au, Gregory Burd, Jun Xu, Ichiro Kikuchi, Tony Yoon | 2012-10-23 |
| 8291290 | Methods and algorithms for joint channel-code decoding of linear block codes | Gregory Burd | 2012-10-16 |
| 8291283 | Layered quasi-cyclic LDPC decoder with reduced-complexity circular shifter | Farshid Rafiee Rad, Nedeljko Varnica | 2012-10-16 |
| 8279546 | Systems and methods for sync mark detection using correlation | Ke Han, Michael Madden | 2012-10-02 |
| 8281213 | LDPC codes and expansion method | Adina Matache, Heng Tang, Gregory Burd, Aditya Ramamoorthy, Jun Xu | 2012-10-02 |
| 8271863 | Forward decision aided nonlinear Viterbi detector | Shaohua Yang | 2012-09-18 |
| 8266495 | Systems and methods for performing concatenated error correction | Xueshi Yang, Seo-How Low | 2012-09-11 |
| 8266484 | Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions | Pantas Sutardja | 2012-09-11 |
| 8259872 | Nonlinear post-processors for channels with signal-dependent noise | Panu Chaichanavong | 2012-09-04 |
| 8255765 | Embedded parity coding for data storage | Engling Yeo, Eugene Pan, Henri Sutioso, Jun Xu, Shaohua Yang +2 more | 2012-08-28 |
| 8255763 | Error correction system using an iterative product code | Shaohua Yang, Gregory Burd, Xueshi Yang, Hongwei Song, Nedeljko Varnica | 2012-08-28 |
| 8255764 | Embedded parity coding for data storage | Engling Yeo, Eugene Pan, Henri Sutioso, Jun Xu, Shaohua Yang +2 more | 2012-08-28 |
| 8245118 | Architecture and control of reed-solomon error identification and evaluation | Ichiro Kikuchi, Siu-Hung Fred Au, Gregory Burd, Jun Xu, Tony Yoon | 2012-08-14 |
| 8230312 | Iterative decoder memory arrangement | Engling Yeo, Panu Chaichanavong, Nedeljko Varnica, Gregory Burd | 2012-07-24 |
| 8228728 | Programming method for multi-level cell flash for minimizing inter-cell interference | Xueshi Yang | 2012-07-24 |
| 8225148 | Systems and methods for achieving higher coding rate using parity interleaving | Heng Tang, Gregory Burd, Panu Chaichanavong | 2012-07-17 |