Issued Patents All Time
Showing 26–40 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9153336 | Decoder parameter estimation using multiple memory reads | Xueshi Yang | 2015-10-06 |
| 9065623 | Mixed mapping for rate compatible trellis coded modulation | Zhengang Chen, Xueshi Yang, Gregory Burd | 2015-06-23 |
| 9009574 | Identification and mitigation of hard errors in memory systems | Gregory Burd, Zhengang Chen | 2015-04-14 |
| 8984378 | Systems and methods for performing multi-state bit flipping in an LDPC decoder | Nedeljko Varnica, Xueshi Yang, Gregory Burd | 2015-03-17 |
| 8943381 | Systems and methods for performing bit flipping in an LDPC decoder | Nedeljko Varnica, Gregory Burd | 2015-01-27 |
| 8913437 | Inter-cell interference cancellation | Zhengang Chen, Gregory Burd | 2014-12-16 |
| 8885415 | Determining optimal reference voltages for progressive reads in flash memory systems | Xueshi Yang | 2014-11-11 |
| 8875000 | Methods and systems systems for encoding and decoding in trellis coded modulation systems | Xueshi Yang | 2014-10-28 |
| 8825945 | Mapping different portions of data to different pages of multi-level non-volatile memory | Xueshi Yang, Gregory Burd | 2014-09-02 |
| 8694868 | Systems and methods for performing multi-state bit flipping in an LDPC decoder | Nedeljko Varnica, Xueshi Yang, Gregory Burd | 2014-04-08 |
| 8681564 | Systems and methods for generating soft information in NAND flash | Zhengang Chen, Gregory Burd, Xueshi Yang | 2014-03-25 |
| 8667361 | Systems and methods for performing bit flipping in an LDPC decoder | Nedeljko Varnica, Gregory Burd | 2014-03-04 |
| 8576625 | Decoder parameter estimation using multiple memory reads | Xueshi Yang | 2013-11-05 |
| 8531888 | Determining optimal reference voltages for progressive reads in flash memory systems | Xueshi Yang | 2013-09-10 |
| 8458556 | Low complexity finite precision decoders and apparatus for LDPC codes | Shiva Kumar Planjery, Bane Vasic, David Declercq | 2013-06-04 |