MC

Michael D. Cusack

Disney: 8 patents #911 of 6,686Top 15%
RTX (Raytheon): 5 patents #2,369 of 15,912Top 15%
AP Avago Technologies General Ip (Singapore) Pte.: 3 patents #357 of 2,004Top 20%
AP Avago Technologies Ecbu Ip Pte.: 1 patents #24 of 98Top 25%
BU Burroughs: 1 patents #265 of 604Top 45%
AU Analog Devices International Unlimited: 1 patents #275 of 574Top 50%
Overall (All Time): #222,884 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9986639 Vertical magnetic barrier for integrated electronic module and related methods Aldrick S. Limjoco, Donal O'Sullivan, Patrick J. Meehan, Thomas Conway 2018-05-29
D728093 Enteral feeding device Renae Moomjian, Karl Sprague, James Nelson, Richard G. Swanson, Lawrence Trujillo 2015-04-28
8269334 Multichip package leadframe including electrical bussing 2012-09-18
8039318 System and method for routing signals between side-by-side die in lead frame type system in a package (SIP) devices Randall D. Briggs 2011-10-18
8021928 System and method for routing supply voltages or other signals between side-by-side die and a lead frame for system in a package (SIP) devices Randall D. Briggs 2011-09-20
7977773 Leadframe including die paddle apertures for reducing delamination 2011-07-12
7902655 Multichip package leadframe including electrical bussing 2011-03-08
7800205 Quad flat pack (QFP) package and flexible power distribution method therefor Thomas Omega Wheless, Jr., Randall D. Briggs 2010-09-21
7745263 System and method for routing supply voltages or other signals between side-by-side die and a lead frame for system in a package (SIP) devices Randall D. Briggs 2010-06-29
7629675 System and method for routing signals between side-by-side die in lead frame type system in a package (SIP) devices Randall D. Briggs 2009-12-08
7495320 System and method for providing a power bus in a wirebond leadframe package 2009-02-24
7446677 Method and apparatus for optically detecting selections made on an input device Steven F. Wald 2008-11-04
7443011 System and method for routing supply voltages or other signals between side-by-side die and a lead frame for system in a package (SIP) devices Randall D. Briggs 2008-10-28
7202546 Integrated circuit with copper interconnect and top level bonding/interconnect layer Salvador Salcido, Michael Kelly, Ravindhar K. Kaw 2007-04-10
4959706 Integrated circuit having an improved bond pad Michael Hagen, James E. Larkin 1990-09-25
4875138 Variable pitch IC bond pad arrangement 1989-10-17
4753820 Variable pitch IC bond pad arrangement 1988-06-28
4730160 Programmable thermal emulator test die Christopher A. Freymuth 1988-03-08
4711700 Method for densifying leadframe conductor spacing 1987-12-08
4463892 Method for manufacturing IC packages Kenneth B. Turnbaugh 1984-08-07