Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7293120 | DMA module having plurality of first addressable locations and determining if first addressable locations are associated with originating DMA process | — | 2007-11-06 |
| 5912581 | Spurious-emission-reducing terminal configuration for an integrated circuit | Ulrich Theus | 1999-06-15 |
| 5608346 | MOS driver circuit for suppressing interference by preventing shunt currents | — | 1997-03-04 |
| 5451861 | Method of setting the output current of a monolithic integrated pad driver | — | 1995-09-19 |
| 5326994 | Protective circuit for protecting contacts of monolithic integrated circuits by preventing parasitic latch up with other integrated circuit elements | Wilfried W. Gehrig | 1994-07-05 |
| 4922139 | Filter circuit for generating a VCO control voltage responsive to the output signals from a frequency/phase discriminator | — | 1990-05-01 |
| 4882610 | Protective arrangement for MOS circuits | Ulrich Theus | 1989-11-21 |
| 4803657 | Serial first-in-first-out (FIFO) memory and method for clocking the same | Ulrich Theus | 1989-02-07 |
| 4750158 | Integrated matrix of nonvolatile, reprogrammable storage cells | Thomas Fischer | 1988-06-07 |
| 4742253 | Integrated insulated-gate field-effect transistor circuit for evaluating the voltage of a node to be sampled against a fixed reference voltage | — | 1988-05-03 |
| 4733394 | Electrically programmable semiconductor memory showing redundance | — | 1988-03-22 |
| 4597064 | Electrically programmable memory matrix | — | 1986-06-24 |
| 4527256 | Electrically erasable memory matrix (EEPROM) | — | 1985-07-02 |
| 4524429 | Integrated memory matrix comprising nonvolatile reprogrammable storage cells | — | 1985-06-18 |
| 4502131 | Electrically programmable memory matrix | — | 1985-02-26 |
| 4459608 | Reprogrammable semiconductor read-only memory of the floating-gate type | Adolf Scheibe | 1984-07-10 |
| 4458338 | Circuit for checking memory cells of programmable MOS-integrated semiconductor memories | Hans Moormann, Lothar Schrader | 1984-07-03 |
| 4435789 | Circuit for a read-only memory organized in rows and columns to prevent bit line potentials from dropping | Hans Moormann, Lothar Schrader | 1984-03-06 |
| 4388541 | Circuit arrangement with MOS-transistors for the rapid evaluation of the logic state of a sampling node | — | 1983-06-14 |