Issued Patents All Time
Showing 51–75 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9547359 | Dynamic system management communication path selection | Vijay Nijhawan | 2017-01-17 |
| 9436256 | Dynamic CPU voltage regulator phase shedding | — | 2016-09-06 |
| 9274581 | Date adjusted power budgeting for an information handling system | Stuart Allen Berke | 2016-03-01 |
| 9261945 | Dynanmic peak power limiting to processing nodes in an information handling system | Mukund P. Khatri, Binay A. Kuruvila | 2016-02-16 |
| 9239601 | Power supply unit (PSU) right-sizing that supports power transients, with mechanism for dynamic curtailment of power transients during a PSU failure | Douglas Evan Messick, Kyle E. Cross | 2016-01-19 |
| 9146599 | Dynamic system management communication path selection | Vijay Nijhawan | 2015-09-29 |
| 9098277 | Information handling system configuration for power system output capability | — | 2015-08-04 |
| 9075595 | Power excursion warning system | — | 2015-07-07 |
| 8924750 | Dynamic CPU voltage regulator phase shedding | — | 2014-12-30 |
| 8028182 | Dynamic CPU voltage regulator phase shedding | — | 2011-09-27 |
| 7406038 | System and method for expansion of computer network switching system without disruption thereof | Mark Lyndon Oelke, Sompong Paul Olarig, Gary B. Kotzur, Matthew J. Schumacher | 2008-07-29 |
| 7296093 | Network processor interface system | Sompong Paul Olarig, Mark Lyndon Oelke, Gary B. Kotzur | 2007-11-13 |
| 7145914 | System and method for controlling data paths of a network processor subsystem | Sompong Paul Olarig, Mark Lyndon Oelke | 2006-12-05 |
| 7085846 | Buffer to buffer credit flow control for computer network | Mark Lyndon Oelke, Sompong Paul Olarig | 2006-08-01 |
| 6865647 | Dynamic cache partitioning | Sompong Paul Olarig, Phillip M. Jones | 2005-03-08 |
| 6792553 | CPU power sequence for large multiprocessor systems | Clarence Y. Mar, Sompong Paul Olarig | 2004-09-14 |
| 6662272 | Dynamic cache partitioning | Sompong Paul Olarig, Phillip M. Jones | 2003-12-09 |
| 6631440 | Method and apparatus for scheduling memory calibrations based on transactions | Sompong Paul Olarig | 2003-10-07 |
| 6564288 | Memory controller with temperature sensors | Sompong Paul Olarig | 2003-05-13 |
| 6493836 | Method and apparatus for scheduling and using memory calibrations to reduce memory errors in high speed memory devices | Sompong Paul Olarig | 2002-12-10 |
| 6484232 | Adaptive calibration technique for high speed memory devices | Sompong Paul Olarig | 2002-11-19 |
| 6467048 | Apparatus, method and system for using cache memory as fail-over memory | Sompong Paul Olarig, Christopher M. Carbajal | 2002-10-15 |
| 6370657 | Hot processor swap in a multiprocessor personal computer system | Kenneth A. Jansen, Sompong Paul Olarig | 2002-04-09 |
| 6370656 | Computer system with adaptive heartbeat | Sompong Paul Olarig | 2002-04-09 |
| 6360333 | Method and apparatus for determining a processor failure in a multiprocessor computer | Kenneth A. Jansen, Sompong Paul Olarig | 2002-03-19 |