Issued Patents All Time
Showing 26–50 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8645621 | Block mapping circuit and method for memory device | — | 2014-02-04 |
| 8630111 | Memory devices and methods for high random transaction rate | Bruce Barbara, John Marino | 2014-01-14 |
| 8595398 | Multi-port memory devices and methods | — | 2013-11-26 |
| 8572320 | Memory devices and systems including cache devices for memory modules | — | 2013-10-29 |
| 8570790 | Memory devices and methods for high random transaction rate | Bruce Barbara, John Marino | 2013-10-29 |
| 8315269 | Device, method, and protocol for data transfer between host device and device having storage interface | Jagadeesan Rajamanickam, Stephen Henry Kolokowsky, Pradeep Kumar Bajpai | 2012-11-20 |
| 8230167 | Block mapping circuit and method for memory device | — | 2012-07-24 |
| 8122189 | Methods for logically combining range representation values in a content addressable memory | — | 2012-02-21 |
| 8069436 | Providing hardware independence to automate code generation of processing device firmware | Warren Snyder, Kenneth Y. Ogami, Mark Hastings | 2011-11-29 |
| 8060708 | Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory | Dinesh Ramanathan, Alakesh Chetia, Herve Jacques Clement Letourneur, Donald W. Smith, Manoj Gujral | 2011-11-15 |
| 8037228 | Bridge device with page-access based processor interface | Jagadeesan Rajamanickam | 2011-10-11 |
| 8018751 | Ternary content addressable memory (TCAM) cells with low signal line numbers | Andrew Wright, Bin Jiang, Bartosz Piotr BANACHOWICZ | 2011-09-13 |
| 7814266 | Partial row expansion by logically combining range representation values in content addressable memory | — | 2010-10-12 |
| 7813155 | Content addressable memory (CAM) cell having column-wise conditional data pre-write | — | 2010-10-12 |
| 7814268 | Row expansion reduction by inversion for range representation in ternary content addressable memories | — | 2010-10-12 |
| 7730268 | Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory | Dinesh Ramanathan, Alakesh Chetia, Herve Jacques Clement Letourneur, Donald W. Smith, Manoj Gujral | 2010-06-01 |
| 7570503 | Ternary content addressable memory (TCAM) cells with low signal line numbers | Andrew Wright, Bin Jiang, Bartosz Piotr BANACHOWICZ | 2009-08-04 |
| 7474545 | Soft priority circuit and method for content addressable memory (CAM) device | — | 2009-01-06 |
| 7450409 | Content addressable memory (CAM) cell having column-wise conditional data pre-write | — | 2008-11-11 |
| 7447052 | Method and device for limiting current rate changes in block selectable search engine | — | 2008-11-04 |
| 7436688 | Priority encoder circuit and method | — | 2008-10-14 |
| 7417882 | Content addressable memory device | — | 2008-08-26 |
| 7391973 | Two-stage gain equalizer | Robert W. Corrigan | 2008-06-24 |
| 7366830 | Row expansion reduction by inversion for range representation in ternary content addressable memories | — | 2008-04-29 |
| 7346823 | Automatic built-in self-test of logic with seeding from on-chip memory | Andrew Wright | 2008-03-18 |