Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10303610 | High-bandwidth prefetcher for high-bandwidth memory | Sanyam Mehta, Daniel Jonathan Ernst, Heidi Lynn Poxon, Luiz DeRose | 2019-05-28 |
| 9946654 | High-bandwidth prefetcher for high-bandwidth memory | Sanyam Mehta, Daniel Jonathan Ernst, Heidi Lynn Poxon, Luiz DeRose | 2018-04-17 |
| 8924654 | Multistreamed processor vector packing method and apparatus | Vincent J. Graziano | 2014-12-30 |
| 8601236 | Configurable vector length computer processor | Gregory J. Faanes, Eric P. Lundberg, Abdulla M. Bataineh, Timothy J. Johnson, Michael Allen Parker +2 more | 2013-12-03 |
| 8307194 | Relaxed memory consistency model | Steven L. Scott, Gregory J. Faanes, Brick Stephenson, William T. Moore | 2012-11-06 |
| 7793073 | Method and apparatus for indirectly addressed vector load-add-store across multi-processors | — | 2010-09-07 |
| 7503048 | Scheduling synchronization of programs running as streams on multiple processors | Kitrick B. Sheets, Josh D. Williams, Jonathan Gettler, Steve Piatz, Andrew B. Hastings +3 more | 2009-03-10 |
| 7437521 | Multistream processing memory-and barrier-synchronization method and apparatus | Steven L. Scott, Gregory J. Faanes, Brick Stephenson, William T. Moore | 2008-10-14 |
| 7421565 | Method and apparatus for indirectly addressed vector load-add -store across multi-processors | — | 2008-09-02 |
| 7366873 | Indirectly addressed vector load-operate-store method and apparatus | — | 2008-04-29 |
| 7343364 | Rules-based system architecture and systems using the same | Charles Bram, John Emmerichs, Richard Wood, Christopher Parrott | 2008-03-11 |
| 7234027 | Instructions for test & set with selectively enabled cache invalidate | Robert Baird | 2007-06-19 |