Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6104251 | Method and apparatus for providing transient suppression in a central processor unit (CPU) phase locked loop clock (PLL) clock signal synthesis circuit | Delvan A. Ramey | 2000-08-15 |
| 5682118 | Circuit for controlling the voltages between well and sources of the transistors of and MOS logic circuit, and system for slaving the power supply to the latter including the application thereof | Matthijs Pardoen | 1997-10-28 |