Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Michael Laor — 20 Patents

Cisco: 15 patents #864 of 13,007Top 7%
CSCompass Electro Optical Systems: 4 patents #6 of 22Top 30%
Oracle: 1 patents #8,339 of 14,854Top 60%
Overall (All Time): #214,803 of 4,157,543Top 6%
20 Patents All Time
Michael Laor has been granted 20 US patents while listed as an inventor at Cisco. The first was granted in 2000 and the most recent in June 2016. Michael Laor ranks #214,803 of 4,157,543 US inventors in our database (top 5.2%). Patent records list Michael Laor in Jerusalem, CA, IL.

Issued Patents All Time

Showing 1–20 of 20 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9363173 Router and switch architecture Eyal Oren, Vladimir Miliavsky 2016-06-07
9304272 EO device for processing data signals Michael Mesh 2016-04-05
8665875 Pipelined packet switching and queuing architecture Garry P. Epps 2014-03-04 $69,686,000
8392487 Programmable matrix processor Michael Mesh, Alexander M. Zeltser 2013-03-05
8325403 Optical programmable matrix processor Michael Mesh, Alexander M. Zeltser 2012-12-04
8018937 Pipelined packet switching and queuing architecture Garry P. Epps 2011-09-13 $27,658,000
7675926 Hierarchical QoS behavioral model Robert Olsen, Clarence Filsfils 2010-03-09 $34,761,000
7643486 Pipelined packet switching and queuing architecture David Belz, Garry P. Epps, Eyal Oren 2010-01-05 $31,506,000
7554907 High-speed hardware implementation of RED congestion control algorithm Garry P. Epps 2009-06-30 $51,994,000
7304999 Methods and apparatus for processing packets including distributing packets across multiple packet processing engines and gathering the processed packets from the processing engines Vitaly Sukonik, Michael B. Galles, Moshe Voloshin, William N. Eatherton, Rami Zemach +1 more 2007-12-04 $68,277,000
7286525 Synchronous pipelined switch using serial transmission Garry P. Epps 2007-10-23 $59,916,000
6980552 Pipelined packet switching and queuing architecture David Belz, Garry P. Epps, Eyal Oren 2005-12-27 $38,340,000
6977930 Pipelined packet switching and queuing architecture Garry P. Epps 2005-12-20 $39,503,000
6831923 Pipelined multiple issue packet switch Martin Cieslak 2004-12-14 $67,800,000
6813243 High-speed hardware implementation of red congestion control algorithm Garry P. Epps 2004-11-02 $112,865,000
6778546 High-speed hardware implementation of MDRR algorithm over a large number of queues Garry P. Epps 2004-08-17 $74,405,000
6731644 Flexible DMA engine for packet header modification Garry P. Epps 2004-05-04 $132,091,000
6721316 Flexible engine and data structure for packet header processing Garry P. Epps 2004-04-13 $94,630,000
6424649 Synchronous pipelined switch using serial transmission Garry P. Epps 2002-07-23 $274,895,000
6147996 Pipelined multiple issue packet switch Martin Cieslak 2000-11-14 $1,376,260,000