YG

Yogesh Goel

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
SY Synopsys: 1 patents #1,143 of 2,302Top 50%
📍 Fremont, CA: #4,197 of 9,298 inventorsTop 50%
🗺 California: #149,087 of 386,348 inventorsTop 40%
Overall (All Time): #1,489,717 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
9589084 Method and system for reproducing prototyping failures in emulation Helena Krupnova 2017-03-07
8161439 Method and apparatus for processing assertions in assertion-based verification of a logic design Amy Lim, Ping-Sheng Tseng 2012-04-17
7480606 VCD-on-demand system and method Ping-Sheng Tseng, Kun-Hsu Shen 2009-01-20