TK

Taranjit Singh Kukal

CS Cadence Design Systems: 35 patents #10 of 2,263Top 1%
Overall (All Time): #98,100 of 4,157,543Top 3%
35
Patents All Time

Issued Patents All Time

Showing 26–35 of 35 patents

Patent #TitleCo-InventorsDate
8732651 Logical design flow with structural compatability verification Nikhil Gupta, Steve Durrill, Vikrant Khanna, Dingru Xiao 2014-05-20
8656329 System and method for implementing power integrity topology adapted for parametrically integrated environment Feras Al-Hawari, Dennis C. Nagle, Raymond Komow, Jilin Tan 2014-02-18
8645894 Configuration and analysis of design variants of multi-domain circuits Amit Chopra, Raja Vitra 2014-02-04
8566767 System and method for parametric intercoupling of static and dynamic analyses for synergistic integration in electronic design automation Heiko Dudek, Jerry A. Long, Chris Banton 2013-10-22
8521483 Method and apparatus for concurrent design of modules across different design entry tools targeted to single simulation Steven R. Durrill 2013-08-27
8452582 System and method for adapting behavioral models to fluctuations in parametrically integrated environment Feras Al-Hawari, Dennis C. Nagle, Raymond Komow, Jilin Tan 2013-05-28
8316342 Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layout Chris Cheung, Vikas Kohli, Keith L. Felton, Frank X. Farmar, Steven R. Durrill 2012-11-20
8286110 System and method for adapting electrical integrity analysis to parametrically integrated environment Feras Al-Hawari, Dennis C. Nagle, Raymond Komow, Jilin Tan 2012-10-09
8145458 Method and system for automatic stress analysis of analog components in digital electronic circuit Sankaran Dharmarajan 2012-03-27
7490309 Method and system for automatically optimizing physical implementation of an electronic circuit responsive to simulation analysis Alok Tripathi 2009-02-10