TS

Tamires Vargas Campanema Franco Santos

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 Belo Horizonte, BR: #105 of 416 inventorsTop 30%
Overall (All Time): #2,974,588 of 4,157,543Top 75%
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Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
9817930 Method, system, and computer program product for verifying an electronic circuit design with a graph-based proof flow Caio Araújo Teixeira Campos, Andrea Iabrudi Tavares, Fabiano Peixoto, Claudionor Coelho 2017-11-14