NA

Narain D. Arora

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 San Jose, CA: #14,517 of 32,062 inventorsTop 50%
🗺 California: #149,087 of 386,348 inventorsTop 40%
Overall (All Time): #1,594,672 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
7088121 Non-contact method and apparatus for on-line interconnect characterization in VLSI circuits Rimma A. Pirogova 2006-08-08
7089516 Measurement of integrated circuit interconnect process parameters Li Song, Aki Fujimura 2006-08-08
5999010 Method of measuring interconnect coupling capacitance in an IC chip Jian Wang 1999-12-07