MT

Marat Teplitsky

CS Cadence Design Systems: 6 patents #235 of 2,263Top 15%
Overall (All Time): #843,155 of 4,157,543Top 25%
6
Patents All Time

Issued Patents All Time

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
9582406 Method and system for automatically generating executable system-level tests Matan Vax, Amit Metodi 2017-02-28
9514035 Coverage driven generation of constrained random stimuli Raz Azaria, Amit Metodi, Yael Kinderman 2016-12-06
9239773 Method and system for debugging a program that includes declarative code and procedural code Reuven Naveh, Rotem Gubes, Raz Azaria 2016-01-19
9189743 System, method, and computer program product for constraint solving Efrat Gavish, Kalev Alpernas 2015-11-17
8719771 Method and system for test reduction and analysis Meir Ovadia, Rodion Melnikov 2014-05-06
8156474 Automation of software verification Meir Ovadia, Noa Gradovich 2012-04-10