KA

Kalev Alpernas

CS Cadence Design Systems: 3 patents #541 of 2,263Top 25%
📍 Lod, IL: #90 of 320 inventorsTop 30%
Overall (All Time): #1,498,957 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
9792402 Method and system for debugging a system on chip under test Meir Ovadia 2017-10-17
9244814 Enriched log viewer Nadav Chazan, Noam Garber, Roman (Reuven) Shenkar, Tal Tabakman 2016-01-26
9189743 System, method, and computer program product for constraint solving Marat Teplitsky, Efrat Gavish 2015-11-17