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Manish Baronia

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
Overall (All Time): #3,192,835 of 4,157,543Top 80%
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Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
8095900 Achieving clock timing closure in designing an integrated circuit Sourav Kumar Sircar 2012-01-10