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Jinduo Sun

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
Overall (All Time): #1,996,597 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
9852258 Method and system for implementing a requirements driven closed loop verification cockpit for analog circuits Paul C. Foster, Walter E. Hartong 2017-12-26
8943450 Model based analog block coverage system Walter E. Hartong, Paul C. Foster 2015-01-27