GA

G. B. Ashok

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
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Patent #TitleCo-InventorsDate
9026966 Co-simulation methodology to address performance and runtime challenges of gate level simulations with, SDF timing using emulators Naresh Ramachandran, Ping-Sheng Tseng 2015-05-05