EN

Eric Nequist

CS Cadence Design Systems: 28 patents #15 of 2,263Top 1%
XC Xcelsis: 6 patents #7 of 19Top 40%
AS Adeia Semiconductor: 2 patents #9 of 14Top 65%
📍 Monte Sereno, CA: #23 of 229 inventorsTop 15%
🗺 California: #12,730 of 386,348 inventorsTop 4%
Overall (All Time): #89,395 of 4,157,543Top 3%
37
Patents All Time

Issued Patents All Time

Showing 26–37 of 37 patents

Patent #TitleCo-InventorsDate
7698666 Method and system for model-based design and layout of an integrated circuit Richard Brashears 2010-04-13
7665045 Method and mechanism for identifying and tracking shape connectivity 2010-02-16
7657860 Method and system for implementing routing refinement and timing convergence Richard Brashears 2010-02-02
7614028 Representation, configuration, and reconfiguration of routing method and system Richard Brashears 2009-11-03
7590955 Method and system for implementing layout, placement, and routing with merged shapes Richard Brashears 2009-09-15
7516433 Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit Steven Lee Pucci 2009-04-07
7461359 Method and mechanism for determining shape connectivity 2008-12-02
7100128 Zone tree method and mechanism Jeffrey S. Salowe, Steven Lee Pucci 2006-08-29
7100129 Hierarchical gcell method and mechanism Jeffrey S. Salowe 2006-08-29
7096445 Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit Steven Lee Pucci 2006-08-22
6983440 Shape abstraction mechanism 2006-01-03
6981235 Nearest neighbor mechanism Jeffrey S. Salowe, Steven Lee Pucci 2005-12-27