DD

Doug Den Dulk

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
Overall (All Time): #2,068,144 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
8397194 Layout versus schematic error system and method Prasanti Uppaluri 2013-03-12
8181137 Layout versus schematic error system and method Prasanti Uppaluri 2012-05-15