DG

Dhananjay Kumar Griyage

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
MG Mentor Graphics: 1 patents #345 of 698Top 50%
Overall (All Time): #1,940,351 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10325055 Signal integrity delay utilizing a window bump-based aggressor alignment scheme Mohan Govindaraj 2019-06-18
9003342 Lumped aggressor model for signal integrity timing analysis Igor Keller, Jijun Chen 2015-04-07