CL

Chi-Yuan Lo

CS Cadence Design Systems: 3 patents #541 of 2,263Top 25%
AT AT&T: 2 patents #7,280 of 18,772Top 40%
📍 Berkeley Heights, NJ: #327 of 1,035 inventorsTop 35%
🗺 New Jersey: #16,490 of 69,400 inventorsTop 25%
Overall (All Time): #1,002,760 of 4,157,543Top 25%
5
Patents All Time

Issued Patents All Time

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
8984468 Method to adaptively calculate resistor mesh in IC designs Shun-Lin Su, Yue Shu 2015-03-17
8701066 Extracting capacitance and resistance from FinFET devices Mikhail Khapaev 2014-04-15
8689157 Extracting capacitance and resistance from FinFET devices Mikhail Khapaev 2014-04-01
5613102 Method of compressing data for use in performing VLSI mask layout verification Kuang-Wei Chiang, Doowan Paik, Shun-Lin Su 1997-03-18
5229231 Method of integrated circuit manufacturing including cell assembly Debaprosad Dutt 1993-07-20