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Bassilios Petrakis

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 San Jose, CA: #22,480 of 32,062 inventorsTop 75%
🗺 California: #247,236 of 386,348 inventorsTop 65%
Overall (All Time): #3,132,577 of 4,157,543Top 80%
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Issued Patents All Time

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
8875077 Fault sensitivity analysis-based cell-aware automated test pattern generation flow Donald J. O'Riordan, Kevin Chou 2014-10-28