AV

Avnish Varma

CS Cadence Design Systems: 3 patents #541 of 2,263Top 25%
📍 Noida, IN: #149 of 795 inventorsTop 20%
Overall (All Time): #1,444,102 of 4,157,543Top 35%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
10540464 Critical path aware voltage drop analysis of an integrated circuit Suketu Desai, Anshu Mani, Apurva H. Soni, Shivani Sharma, Xin Gu 2020-01-21
10515174 Interface modeling for power analysis of an integrated circuit Rishabh, Xin Gu 2019-12-24
10387595 Systems and methods for modeling integrated clock gates activity for transient vectorless power analysis of an integrated circuit Anshu Mani, Suketu Desai 2019-08-20