AF

Andrey Freidlin

CS Cadence Design Systems: 3 patents #541 of 2,263Top 25%
📍 Surovikino, RU: #1 of 1 inventorsTop 100%
Overall (All Time): #1,427,326 of 4,157,543Top 35%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
10909301 Method and apparatus for determining waiver applicability conditions and applying the conditions to multiple errors or warnings in physical verification tools Alexey Kalinov, Douglas M. Den Dulk 2021-02-02
10216888 Constraint validation process Mikhail Kanshin, Alexey Kalinov, Andrei Savelev, Douglas M. Den Dulk, Wojciech Wojciak 2019-02-26
10210301 System and method for implementing and validating star routing for power connections at chip level Ankur Chavhan, Devesh Jain, Behnam Farhat, Sundararajan Shanmugam, Susan ZHANG 2019-02-19