Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11436186 | High throughput processors | Daniel Roig, Gnanashanmugam Elumalai | 2022-09-06 |
| 10970245 | Processor with reconfigurable pipelined core and algorithmic compiler | — | 2021-04-06 |
| 10515041 | Processor with reconfigurable pipelined core and algorithmic compiler | — | 2019-12-24 |
| 7800856 | Disk drive flushing write cache to a nearest set of reserved tracks during a power failure | George J. Bennett, Dean M. Jenkins | 2010-09-21 |
| 7031902 | Presilicon disk model for design, development and validation | — | 2006-04-18 |
| 4713608 | Apparatus for providing cost efficient power measurement | John D. Faivre, Fah Rakpongs | 1987-12-15 |
| 4514824 | Byte-oriented line adapter system | Richard A. Loskorn, Philip D. Biehl | 1985-04-30 |
| 4510603 | Testing system for reliable access times in ROM semiconductor memories | — | 1985-04-09 |
| 4507732 | I/O subsystem using slow devices | Brian K. Forbes | 1985-03-26 |
| 4456970 | Interrupt system for peripheral controller | Brian K. Forbes | 1984-06-26 |
| 4455622 | Bit-oriented line adapter system | Richard A. Loskorn, Philip D. Biehl | 1984-06-19 |
| 4430710 | Subsystem controller | Craig W. Harris, Ronald D. Mathews | 1984-02-07 |
| 4430735 | Apparatus and technique for testing IC memories | — | 1984-02-07 |
| 4429389 | Test pattern address generator | — | 1984-01-31 |
| 4428043 | Data communications network | Craig W. Harris, Ronald D. Mathews | 1984-01-24 |
| 4379265 | Dual clocking time delay generation circuit | — | 1983-04-05 |
| 4379328 | Linear sequencing microprocessor facilitating | Brian K. Forbes | 1983-04-05 |
| 4374416 | Linear sequencing microprocessor having word and byte handling | Brian K. Forbes | 1983-02-15 |
| 4374418 | Linear microsequencer unit cooperating with microprocessor system having dual modes | Brian K. Forbes | 1983-02-15 |
| 4371931 | Linear micro-sequencer for micro-processor system utilizing specialized instruction format | Brian K. Forbes | 1983-02-01 |
| 4301505 | Microprocessor having word and byte handling | Brian K. Forbes | 1981-11-17 |
| 4293909 | Digital system for data transfer using universal input-output microprocessor | Brian K. Forbes | 1981-10-06 |
| 4292667 | Microprocessor system facilitating repetition of instructions | Brian K. Forbes | 1981-09-29 |
| 4291372 | Microprocessor system with specialized instruction format | Brian K. Forbes | 1981-09-22 |
| 4290106 | Microprocessor system with source address selection | Brian K. Forbes | 1981-09-15 |