Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8149904 | Asymmetric digital subscriber line modem apparatus and methods therefor | Haixiang Liang, Kevin H. Peterson, Yuanjie Chen, Alan Corry, Nino P. Ferrario +8 more | 2012-04-03 |
| 7809902 | Method and system for copying DMA with separate strides by a modulo-n counter | Jeff Z. Guan, Lin Yin | 2010-10-05 |
| 7482964 | Switching between lower and higher power modes in an ADC for lower/higher precision operations | Srinivasa H. Garlapati, Paul Lettieri, Jason A. Trachewsky, Tom W. Kwan | 2009-01-27 |
| 7184468 | Method and system for implementing a conditional one's complement of partial address | — | 2007-02-27 |
| 7177988 | Method and system for synchronizing processor and DMA using ownership flags | Jeff Z. Guan, Gong-san Yu | 2007-02-13 |
| 7146391 | Method and system for implementing SLICE instructions | Haixiang Liang, Yuanjie Chen | 2006-12-05 |
| 7142139 | Powering down of DAC and ADC for receive/transmit modes of operation in a wireless device | Venkat Kodavati, Gouri Pidugu, Srinivasa H. Garlapati | 2006-11-28 |
| 7116259 | Switching between lower and higher power modes in an ADC for lower/higher precision operations | Srinivasa H. Garlapati, Paul Lettieri, Jason A. Trachewsky, Tom W. Kwan | 2006-10-03 |
| 7079058 | Powering down of DAC and ADC for receive/transmit modes of operation in a wireless device | Venkat Kodavati, Gouri Pidugu, Srinivasa H. Garlapati | 2006-07-18 |
| 6721878 | Low-latency interrupt handling during memory access delay periods in microprocessors | Somnath Paul | 2004-04-13 |
| 6704863 | Low-latency DMA handling in pipelined processors | Somnath Paul | 2004-03-09 |
| 6075906 | System and method for the scaling of image streams that use motion vectors | Stephen C. Fenwick, Timothy J. Van Hook | 2000-06-13 |