Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6933557 | Fowler-Nordheim block alterable EEPROM memory cell | — | 2005-08-23 |
| 6919242 | Mirror image memory cell transistor pairs featuring poly floating spacers | — | 2005-07-19 |
| 6905926 | Method of making nonvolatile transistor pairs with shared control gate | — | 2005-06-14 |
| 6888192 | Mirror image non-volatile memory cell transistor pairs with single poly layer | — | 2005-05-03 |
| 6846709 | Vertical gate CMOS with lithography-independent gate length | — | 2005-01-25 |
| 6841823 | Self-aligned non-volatile memory cell | Alan Renninger | 2005-01-11 |
| 6831325 | Multi-level memory cell with lateral floating spacers | — | 2004-12-14 |
| 6822285 | EEPROM with multi-member floating gate | — | 2004-11-23 |
| 6690059 | Nanocrystal electron device | — | 2004-02-10 |
| 6624027 | Ultra small thin windows in floating gate transistors defined by lost nitride spacers | Eleonore Daemen, Alan Renninger | 2003-09-23 |
| 6624029 | Method of fabricating a self-aligned non-volatile memory cell | Alan Renninger | 2003-09-23 |
| 6596604 | Method of preventing shift of alignment marks during rapid thermal processing | Michael Whiteman | 2003-07-22 |
| 6486031 | Method of making an EEPROM cell with asymmetric thin window | — | 2002-11-26 |
| 6479351 | Method of fabricating a self-aligned non-volatile memory cell | Alan Renninger | 2002-11-12 |
| 6369422 | Eeprom cell with asymmetric thin window | — | 2002-04-09 |
| 6346443 | Non-volatile semiconductor memory device | — | 2002-02-12 |
| 5851892 | Fabrication sequence employing an oxide formed with minimized inducted charge and/or maximized breakdown voltage | Joseph M. McRae | 1998-12-22 |
| 5635422 | Diffusing dopants into a semiconductor wafer | — | 1997-06-03 |