Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Patrick Yin — 11 Patents

ATAspec Technology: 7 patents #1 of 3Top 35%
LSLsi: 3 patents #1,320 of 3,238Top 45%
FIFairchild Camera & Instrument: 1 patents #58 of 173Top 35%
San Jose, CA: #5,902 of 32,062 inventorsTop 20%
California: #56,011 of 386,348 inventorsTop 15%
Overall (All Time): #435,149 of 4,157,543Top 15%
11 Patents All Time
Patrick Yin has been granted 11 US patents while listed as an inventor at Aspec Technology. The first was granted in 1984 and the most recent in October 2001. Patrick Yin ranks #435,149 of 4,157,543 US inventors in our database (top 10.5%). Patent records list Patrick Yin in San Jose, CA, US.

Issued Patents All Time

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
6298469 Method and system for allowing an integrated circuit to be portably generated from one manufacturing process to another 2001-10-02
5723992 Low leakage output driver circuit which can be utilized in a multi-voltage source Craig S. Thrower 1998-03-03
5701021 Cell architecture for mixed signal applications 1997-12-23
5635737 Symmetrical multi-layer metal logic array with extension portions for increased gate density and a testability area 1997-06-03
5493135 Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density 1996-02-20
5463563 Automatic logic model generation from schematic data base Owen S. Bair, Chih-Chung Chen 1995-10-31 $33,645,000
5404034 Symmetrical multi-layer metal logic array with continuous substrate taps 1995-04-04
5384472 Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density 1995-01-24
5278769 Automatic logic model generation from schematic data base Owen S. Bair, Chih-Chung Chen 1994-01-11 $3,507,000
4912344 TTL output stage having auxiliary drive to pull-down transistor 1990-03-27
4465945 Tri-state CMOS driver having reduced gate delay 1984-08-14 $5,815,000