Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density

Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density

US Patent 5493135 · Granted Feb 20, 1996

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and system for allowing an integrated circuit to be portably generated fr2001
Low leakage output driver circuit which can be utilized in a multi-voltage sourc1998
Cell architecture for mixed signal applications1997
Symmetrical multi-layer metal logic array with extension portions for increased 1997
Automatic logic model generation from schematic data base1995
Symmetrical multi-layer metal logic array with continuous substrate taps1995
Symmetrical multi-layer metal logic array with continuous substrate taps and ext1995
Automatic logic model generation from schematic data base1994
TTL output stage having auxiliary drive to pull-down transistor1990
Tri-state CMOS driver having reduced gate delay1984