Issued Patents All Time
Showing 51–61 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6897700 | Amplifier with digital DC offset cancellation feature | Joseph Balardeta | 2005-05-24 |
| 6822483 | No resonance mode bang-bang phase detector | Joseph Balardeta | 2004-11-23 |
| 6744293 | Global clock tree de-skew | Joseph Balardeta | 2004-06-01 |
| 6741108 | Method and circuit to reduce jitter generation in a PLL using a reference quadrupler and an equalizer | Joseph Balardeta, Allen Carl Merrill | 2004-05-25 |
| 6657464 | Method and circuit to reduce jitter generation in a PLL using a reference quadrupler, equalizer, and phase detector with control for multiple frequencies | Joseph Balardeta, Allen Carl Merrill | 2003-12-02 |
| 6642781 | Selectable equalization system and method | Mehmet Mustafa Eker, Joseph Balardeta | 2003-11-04 |
| 6566967 | Configurable triple phase-locked loop circuit and method | Sudhaker Reddy Anumula, Joseph Balardeta, Paul Vanderbilt, Mehmet Mustafa Eker | 2003-05-20 |
| 6545524 | Configurable multiplexing circuit and method | Sudhaker Reddy Anumula, Joseph Balardeta, Paul Vanderbilt, Allen Carl Merrill | 2003-04-08 |
| 6538520 | Methods and apparatus for producing a reference frequency signal with use of a reference frequency quadrupler having frequency selection controls | Allen Carl Merrill, Joseph Balardeta, Mehmet Mustafa Eker | 2003-03-25 |
| 6469574 | Selectable equalization system and method | Mehmet Mustafa Eker, Joseph Balardeta | 2002-10-22 |
| 6121804 | High frequency CMOS clock recovery circuit | Thomas Clark Bryan, Allen Carl Merrill | 2000-09-19 |