| 7286527 |
Method and apparatus for round trip delay measurement in a bi-directional, point-to-point, serial data channel |
Kreg Martin |
2007-10-23 |
| 6373493 |
Hardware graphics accelerator having access to multiple types of memory including cached memory |
Jay B. Rickard |
2002-04-16 |
| 6256710 |
Cache management during cache inhibited transactions for increasing cache efficiency |
Michael J. Dhuey |
2001-07-03 |
| 5901295 |
Address and data bus arbiter for pipelined transactions on a split bus |
— |
1999-05-04 |
| 5845327 |
Cache coherency where multiple processors may access the same data over independent access paths |
Jay B. Rickard, Dale R. Adams |
1998-12-01 |
| 5815676 |
Address bus arbiter for pipelined transactions on a split bus |
— |
1998-09-29 |
| 5812815 |
Address tenure control for cache management wherein bus master addresses are internally latched in a cache controller |
— |
1998-09-22 |
| 5708783 |
Data bus arbiter for pipelined transactions on a split bus |
— |
1998-01-13 |
| 5603007 |
Methods and apparatus for controlling back-to-back burst reads in a cache system |
Michael J. Dhuey |
1997-02-11 |
| 5600802 |
Methods and apparatus for translating incompatible bus transactions |
Michael J. Dhuey |
1997-02-04 |
| 5546547 |
Memory bus arbiter for a computer system having a dsp co-processor |
Michael J. Bowes |
1996-08-13 |
| 5515514 |
Peripheral processor card for upgrading a computer |
Michael J. Dhuey |
1996-05-07 |
| 5500827 |
Method and apparatus for improved DRAM refresh operation |
Michael J. Dhuey |
1996-03-19 |
| 5237573 |
Method and apparatus for selectively switching between input signals |
Michael J. Dhuey |
1993-08-17 |
| 4887240 |
Staggered refresh for dram array |
Timothy L. Garverick, Richard Henderson, Webster B. Meier |
1989-12-12 |
