Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11940491 | Built-in self-test for die-to-die physical interfaces | Arnaud J. Forestier, Vikram Mehta | 2024-03-26 |
| 11899061 | Voltage monitoring circuit for interface | Si Chen, Mansour Keramat, Arnaud J. Forestier | 2024-02-13 |
| 11662380 | Built-in self-test for die-to-die physical interfaces | Arnaud J. Forestier, Vikram Mehta | 2023-05-30 |
| 10515028 | Reference voltage calibration using a qualified weighted average | Robert E. Jeter, Brijesh Tripathi, Kiran B. Kattel, Rakesh L. Notani, Sukalpa Biswas +6 more | 2019-12-24 |
| 10408863 | Reference voltage prediction in memory subsystem | Robert E. Jeter, Rakesh L. Notani | 2019-09-10 |
| 10242723 | Method and apparatus for background memory subsystem calibration | Robert E. Jeter | 2019-03-26 |
| 10241537 | Digital on-chip duty cycle monitoring device | Huaimin Li, Shy Hamami, Pradeep Trivedi, Yaron Cohen | 2019-03-26 |
| 10175905 | Systems and methods for dynamically switching memory performance states | Robert E. Jeter, Liang Deng, Kai Lun Hsiung, Manu Gulati, Rakesh L. Notani +4 more | 2019-01-08 |
| 10083736 | Adaptive calibration scheduling for a memory subsystem based on calibrations of delay applied to data strobe and calibration of reference voltage | Robert E. Jeter, Rakesh L. Notani | 2018-09-25 |
| 10019387 | Reference voltage calibration using a qualified weighted average | Robert E. Jeter, Brijesh Tripathi, Kiran B. Kattel, Rakesh L. Notani, Sukalpa Biswas +6 more | 2018-07-10 |
| 9990973 | Systems and methods using neighboring sample points in memory subsystem calibration | Robert E. Jeter, Rakesh L. Notani | 2018-06-05 |
| 9829966 | Method for preparing a system for a power loss | Manu Gulati, Tristan R. Hudson, Parin Patel | 2017-11-28 |