| 6867780 |
System, method and article of manufacture for allowing direct memory access to graphics vertex data while bypassing a processor |
David B. Kirk, Paolo E. Sabella, Mark J. Kilgard |
2005-03-15 |
| 5802055 |
Method and apparatus for dynamic buffer allocation in a bus bridge for pipelined reads |
William T. Krein, James D. Kelly |
1998-09-01 |
| 5748917 |
Line data architecture and bus interface circuits and methods for dual-edge clocking of data to bus-linked limited capacity devices |
William T. Krein, James D. Kelly |
1998-05-05 |
| 5692137 |
Master oriented bus bridge |
Michael L. Regal |
1997-11-25 |
| 5674077 |
Interleaved connector circuit having increased backplane impedance |
William T. Krein |
1997-10-07 |
| 5630077 |
System and method for coordinating access to a bus |
William T. Krein, James D. Kelly |
1997-05-13 |
| 5590130 |
Bus protocol using separate clocks for arbitration and data transfer |
William T. Krein, James D. Kelly |
1996-12-31 |
| 5557755 |
Method and system for improving bus utilization efficiency |
William T. Krein, James D. Kelly |
1996-09-17 |
| 5473762 |
Method and system for pipelining bus requests |
William T. Krein, James D. Kelly |
1995-12-05 |
| 5410677 |
Apparatus for translating data formats starting at an arbitrary byte position |
Steven Roskowski, Dean Drako |
1995-04-25 |
| 5105424 |
Inter-computer message routing system with each computer having separate routinng automata for each dimension of the network |
Charles L. Seitz |
1992-04-14 |
