| 7358884 |
Methods and systems for implementing a Digital-to-Analog Converter |
Lawrence F. Heyl, David Tupman |
2008-04-15 |
| 5949981 |
Deadlock avoidance in a bridge between a split transaction bus and a single envelope bus |
— |
1999-09-07 |
| 5838955 |
Controller for providing access to a video frame buffer in split-bus transaction environment |
Eric Baden |
1998-11-17 |
| 5828856 |
Dual bus concurrent multi-channel direct memory access controller and method |
Michael J. Bowes |
1998-10-27 |
| 5805927 |
Direct memory access channel architecture and method for reception of network information |
Michael J. Bowes |
1998-09-08 |
| 5793996 |
Bridge for interconnecting a computer system bus, an expansion bus and a video frame buffer |
Eric Baden |
1998-08-11 |
| 5689656 |
Dynamic hierarchical arbitration of computer resource access requests |
Eric Baden |
1997-11-18 |
| 5655151 |
DMA controller having a plurality of DMA channels each having multiple register sets storing different information controlling respective data transfer |
Michael J. Bowes |
1997-08-05 |
| 5640545 |
Frame buffer interface logic for conversion of pixel data in response to data format and bus endian-ness |
Eric Baden |
1997-06-17 |
| 5634013 |
Bus bridge address translator |
Eric Baden |
1997-05-27 |
| 5625778 |
Method and apparatus for presenting an access request from a computer system bus to a system resource with reduced latency |
Eric Baden |
1997-04-29 |
| 5043981 |
Method of and system for transferring multiple priority queues into multiple logical FIFOs using a single physical FIFO |
Farzin Firoozmand |
1991-08-27 |
| 4771264 |
INFO 1 detection |
— |
1988-09-13 |
